The present invention comes within the field of digital transmissions.
It concerns a digital multiplexing device.
The principle of digital multiplexing is known: n digital trains having a given pulse rate and carried by n channels called in-coming channels are multiplexed in time into a single train having a higher pulse rate and carried by a channel called the out-going channel. To effect that multiplexing operation, it is necessary to make the in-coming trains synchronous with one another. These trains are, indeed, generally only plesiochronous, that is, they have a same rated pulse rate but are controlled by independent clocks, which are not synchronized in relation to one another; their pulse rate cannot therefore be strictly equal. These plesiochronous trains are therefore synchronized, all being brought to a same pulse rate slightly more rapid than that which each of them can have. This difference in rate is compensated by the incorporating, in each train, of extra bits, called justification bits or stuffing bits.
On receiving of the out-going channel, a demultiplexer must be able to recognize, in the multiplex (or rapid) train, the justification bits inherent to each one of the in-coming channels and extract them therefrom, in order to able to restore correctly the slow trains. To do this, the justification bits take up, in the multiplex train, quite precise positions and it is necessary to insert, at locations which are also determined, data called "justification indicator data" which make it possible to know if a justification has been effected.
The multiplex train which is at a pulse rate slightly higher than n times the highest pulse rate which the slow trains may have, is articulated, generally, in successive frames, characterized by a particular and repetitive signal, called the frame locking word and composed of a set of ordinated binary elements whose number is definite. Each frame comprises:
Binary elements containing the data to be transmitted, coming from the slow trains; these binary elements will be called "informative bits":
Filling binary elements which comprise:
Systematic binary insertion elements formed by: PA1 The frame locking word with, contingently, service bits and the whole will be designated as the frame beginning "identification character";
The justification indicators inherent to each of the incoming channels;
The contingent justifications for the various in-coming channels.
In known multiplexing systems, n channel elements each receive a slow digital train and set them in synchronism by the adding of justification bits; a multiplexing element sends out, from these synchronized trains, the multiplexed train. The channel elements comprise means for effecting the necessary justifications in the slow trains and inserting the justification indicator bits in the synchronized trains so that these latter, which reach the multiplexing element, be ready to be multiplexed, binary element by binary element (interlacing). To do this, it is necessary for each of the channel elements to receive from the multiplexing element, data concerning the pulse rate of the multiplex train, the frame frequency, the location of the binary justification elements and the location of the binary justification indicator elements assigned to the corresponding in-coming channel.
In such an equipment, the number of connections between the channel elements and the multiplexing element is therefore great, this making wiring difficult for a high in-coming rhythm and a great number of in-coming channels.